RISC-V: fsgnj.d/fmv.d retire without F/D extension

RISC-V: fsgnj.d/fmv.d retire without F/D extension

Rechecked revision

The report was rechecked against the public Unicorn dev branch at 938efd13aeab73155f31cf707a2094c6ccaa36dd.

Problem

trans_fsgnj_d, which also implements the fmv.d alias, lacks the FPU and D extension checks used by neighboring D-extension translators. On UC_CPU_RISCV64_SIFIVE_E51, whose ISA has neither F nor D, the instruction retires and guest execution continues instead of raising an illegal-instruction exception.

Public reproducer

The freestanding witness and runner are available at https://github.com/carlosqwqqwq/unicorn-riscv-repros/tree/main/u020. After building the public dev checkout, run:

LIBUNICORN_PATH=/path/to/unicorn/build ./u020/run.sh

The E51 run must raise UC_ERR_EXCEPTION. A D-enabled control remains legal.

Expected behavior

fsgnj.d and its fmv.d alias require F/D support. QEMU with D disabled rejects the instruction, while a D-enabled CPU executes it.

Root cause and proposed fix

Add REQUIRE_FPU; and REQUIRE_EXT(ctx, RVD); at the start of trans_fsgnj_d, matching the sibling D-extension translators. The focused regression is included in PR #2393.