[Bug] ICM45686: FIFO empty counter keeps increasing with INT1 correctly wired

Describe the bug

Summary

I tested the ICM45686 driver on a real DM-FC01 flight controller based on the fixes from PR #27663.

The ICM45686 interrupt wiring has been checked against both the board schematic and the ICM45686 pin definition. The FIFO threshold interrupt is connected to the correct INT1 pin and the corresponding MCU GPIO.

However, the FIFO empty performance counter continues to increase during normal operation.

Hardware

• Board: DM-FC01
• MCU: STM32H743VIH6
• Sensor: ICM45686
• Interface: SPI4
• SPI chip select: PC13
• PX4 version: 1.16.0
• PX4 commit: fdb504df988eee73e9fd647569bca3d8e754975a
• Test date: 2026-09-18

Interrupt wiring

The physical pin mapping was checked as follows:

• ICM45686 physical pin 4: INT1 / INT
• MCU mapping: INT1 -> PE4

The other interrupt pin is:

• ICM45686 physical pin 9: INT2 / FSYNC / CLKIN
• MCU mapping: INT2 -> PE3

The board driver therefore uses:

SPI::DRDY{GPIO::PortE, GPIO::Pin4}

PR #27663 routes the FIFO threshold interrupt to INT1, so PE4 is the matching DRDY GPIO. PE3/INT2 is not used for this fix.

Test procedure

1. Built the PX4 firmware with the ICM45686 fixes from PR #27663.
2. Flashed the firmware to the real DM-FC01 hardware.
3. Started the sensor on SPI4.
4. Monitored icm45686 status for 10 seconds.
5. Checked listener sensor_gyro 1.

Observed results

Initial status:

SPI Bus: 4
FIFO empty: 2563 events
FIFO overflow: 0 events
FIFO reset: 1 events
bad transfer: 0 events
DRDY missed: 53 events

After approximately 10 seconds:

SPI Bus: 4
FIFO empty: 2756 events
FIFO overflow: 0 events
FIFO reset: 1 events
bad transfer: 0 events
DRDY missed: 56 events

Therefore, during the 10-second observation:

FIFO empty: +193
DRDY missed: +3

The sensor_gyro ICM45686 instance continued publishing data. The observed timestamp_sample was approximately 90–102 microseconds before the publication timestamp, which suggests that the INT1/PE4 timestamp path is active.

Expected behavior

I would expect:

• bad transfer to remain at zero;
• FIFO overflow to remain at zero;
• FIFO empty to remain close to zero during steady-state operation;
• DRDY missed to remain at zero or occur only very rarely.

The persistent increase of FIFO empty appears abnormal, even though the INT1/PE4 interrupt path is working.

Questions

Could this behavior be expected when using a 6400 Hz ODR with a short FIFO batch?

Possible causes I would like to clarify are:

1. Duplicate or early execution caused by the DRDY callback and the watchdog backup schedule;
2. FIFO threshold not being latched in some cases;
3. A timing race between the INT1 status and FIFO_COUNT read;
4. Another expected behavior of the ICM45686 FIFO interrupt mechanism.

What range of FIFO empty events would be considered normal for this driver configuration?

Related to #27663.

Flight Log / Additional Information

No response