Rust 中的 RISC-V 监控程序二进制接口 (RISC-V SBI) 库;在 M 或 HS 模式下运行;对嵌入式 Rust 生态系统提供良好的支持。有关二进制下载,请参阅 prototy
Rust 中的 RISC-V 监控程序二进制接口 (RISC-V SBI) 库;在 M 或 HS 模式下运行;对嵌入式 Rust 生态系统提供良好的支持。有关二进制下载,请参阅 prototy
RISC-V Supervisor Binary Interface (SBI) library in Rust; runs on M-mode or HS mode.
Most users would get RustSBI binary download from the RustSBI Prototyper. Check out the documents here to build or download images for supported platforms.
Boards, SoC vendors and research groups may sometimes provide dedicated RustSBI package for supported platforms. There are packages exists on awesome-rustsbi: it is a curated list of awesome things related to RustSBI, which includes some implementation projects maintained by individuals or the community.
Users on commercial boards may visit implementation specific distribution links depending on the platforms they need, or consult vendors if they provide discrete RustSBI package support.
All crates under library/ support Rust 1.88 or later on their supported targets. Each crate inherits this
minimum supported Rust version (MSRV) from the root Cargo.toml. With both the MSRV and current
stable Rust, CI tests the host-compatible libraries, checks every library on RV64IMAC with all features, and checks the
RV32IMAC-compatible libraries on RV32IMAC.
Repository-wide development, including RustSBI Prototyper, uses the date-pinned nightly toolchain in
rust-toolchain.toml. rustup selects it automatically for commands run in this repository.
If you need to build RustSBI firmware for M-mode, please refer to the RustSBI Prototyper documentation.
RustSBI is usually used as a library or dependency. If you wish to, you may build RustSBI library itself using the following command:
cargo build
The build should finish without any errors.
Building under native platform will allow development of hypervisors and emulators. To check the libraries on RISC-V with stable Rust, install the target for that toolchain and cross-build:
rustup target add --toolchain stable riscv64imac-unknown-none-elf
cargo +stable build --locked --target riscv64imac-unknown-none-elf
The target platform of RISC-V platform firmware is usually a bare metal target.
Under normal circumstances these targets in Rust would start with riscv??- and end with -none-elf.
The repository provides a Docker image for development on hosts that do not match the CI environment.
It includes the pinned nightly toolchain, RISC-V targets, QEMU, U-Boot tools and cargo-binutils.
For a one-off check, run:
docker build -t rustsbi-dev .
docker run --rm -v "$PWD:/workspace" -w /workspace rustsbi-dev cargo check
For an interactive shell, run:
docker run --rm -it -v "$PWD:/workspace" -w /workspace rustsbi-dev bash
The source tree is mounted at /workspace; changes and build artifacts stay on the host.
RustSBI have extensive documents on such purposes! No matter what you are building with it, you will find some documents about RustSBI on bare-metal environments, hypervisors and emulators.
Check it out at RustSBI document main page.
Yes, you can! RustSBI strictly follows RISC-V SBI standard. All features are prepares for all programming languages, as long as they support RISC-V SBI defined calling convention.
If your kernel language supports other SBI implementations, usually it will support RustSBI in the same way.
This project is originally a part of rCore Summer of Code 2020 activities, inspired by MeowSBI and other similar projects. Now it is capable of running rCore-Tutorial and other OS kernels on wide supported RISC-V devices.
There are multiple talks related to RustSBI dated back to Aug 2020. These talks discuss from design and abstraction of RustSBI modules, to actual production and research usage scenario related to RustSBI and RISC-V bootloaders. Public slides and blog articles of these talks are available at RustSBI/slides page.
embedded-hal libraries.Please see our Security Policy for information on how to report security vulnerabilities.
The RustSBI project is sponsored by multiple institutions, companies, and individuals.
Individual sponsors (by order of donation):
| Chao Liu | ||
| (@zevorn) | Zhenchen Wang | |
| (@Plucky923) | Zongyao Chen | |
| (@chenzongyao200127) |
This project is licensed under either of
Documents from RISC-V SBI Specification are used in this project. These documents are (C) RISC-V Foundation under Creative Commons Attribution 4.0 International License (CC-BY 4.0). The full license text is available at https://creativecommons.org/licenses/by/4.0/.
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