AARCH64: 当 Rd == Rm 时,标量 FMIN/FMAX/FMAXNM 计算错误
作者: romanmikhailov创建于 2026年9月4日更新于 2026年9月14日
标签Type: BugFeature: Processor/AARCH64Status: Internal
Describe the bug
The AArch64 SLEIGH semantics for the scalar FMIN/FMAX/FMAXNM instructions write the destination register before reading the second source operand. When an encoding names the same register for both Rd and Rm, the first assignment destroys the operand the subsequent comparison reads, and the instruction is silently mis-lifted.
内容来源: NationalSecurityAgency/ghidra