Python-based Hardware Design Processing Toolkit for Verilog HDL
Python-based Hardware Design Processing Toolkit for Verilog HDL
Python-based Hardware Design Processing Toolkit for Verilog HDL
Copyright 2013, Shinya Takamaeda-Yamazaki and Contributors
Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
If you use Pyverilog in your research, please cite the following paper.
@inproceedings{Takamaeda:2015:ARC:Pyverilog,
title={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},
author={Takamaeda-Yamazaki, Shinya},
booktitle={Applied Reconfigurable Computing},
month={Apr},
year={2015},
pages={451-460},
volume={9040},
series={Lecture Notes in Computer Science},
publisher={Springer International Publishing},
doi={10.1007/978-3-319-16214-0_42},
url={http://dx.doi.org/10.1007/978-3-319-16214-0_42},
}Pyverilog is an open-source hardware design processing toolkit for Verilog HDL. All source codes are written in Python.
Pyverilog includes (1) code parser, (2) dataflow analyzer, (3) control-flow analyzer and (4) code generator. You can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit.
Pyverilog project always welcomes questions, bug reports, feature proposals, and pull requests on GitHub.
Please leave your comment on the issue tracker on GitHub.
Please check "CONTRIBUTORS.md" for the contributors who provided pull requests.
Pyverilog uses pytest for the integration testing. When you send a pull request, please include a testing example with pytest. To write a testing code, please refer the existing testing examples in "tests" directory.
If the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the develop branch by the main committers.
sudo apt install iverilogpip3 install jinja2 plyThese are required for automatic testing of tests. We recommend to install these testing library to verify experimental features.
pip3 install pytest pytest-pythonpathThese are required for graph visualization by dataflow/graphgen.py and controlflow/controlflow_analyzer.py.
sudo apt install graphviz
pip3 install pygraphvizNow you can install Pyverilog using setup.py script:
python3 setup.py installThis software includes various tools for Verilog HDL design.
First, please prepare a Verilog HDL source file as below. The file name is 'test.v'. This sample design adds the input value internally whtn the enable signal is asserted. Then is outputs its partial value to the LED.
module top
(
input CLK,
input RST,
input enable,
input [31:0] value,
output [7:0] led
);
reg [31:0] count;
reg [7:0] state;
assign led = count[23:16];
always @(posedge CLK) begin
if(RST) begin
count 'd0)--> 1
1 --None--> 2
2 --None--> 0
Loop
(0, 1, 2)You got also a png file (top_state.png), if you did not append "--nograph". The picture shows that the graphical structure of the state machine.
Finally, let's try code generation. Please prepare a Python script as below. The file name is 'test.py'. A Verilog HDL code is represented by using the AST classes defined in 'vparser.ast'.
…Please type the command as below at the same directory with Pyverilog.
python3 test.pyThen Verilog HDL code generated from the AST instances is displayed.
module top #
(
parameter DATAWID = 32
)
(
input CLK,
input RST,
output [7:0] led
);
reg [DATAWID-1:0] count;
assign led = count[DATAWID-1:DATAWID-8];
always @(posedge CLK) begin
if(RST) begin
count <= 0;
end else begin
count <= count + 1;
end
end
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