32-bit RISC-V CPU in ~800 lines of C89
RISC-V CPU core written in ANSI C.
Features:
RV32IMAC_Zicsr implementation with M-mode and S-moderiscv-tests/* Memory access callback: data is input/output, return RV_BAD on fault. */
typedef rv_res (*rv_bus_cb)(void *user, rv_u32 addr, rv_u8 *data, rv_u32 is_store, rv_u32 width);
/* Initialize CPU. You can call this again on `cpu` to reset it. */
void rv_init(rv *cpu, void *user, rv_bus_cb bus_cb);
/* Single-step CPU. Returns RV_E* on exception. */
rv_u32 rv_step(rv *cpu);…This repository contains a machine emulator that can use rv to boot Linux.
See tools/linux/README.md.
rvUse riscv-gnu-toolchain with tools/link.ld.
Suggested GCC commandline:
riscv64-unknown-elf-gcc example.S -nostdlib -nostartfiles -Tlink.ld -march=rv32imac -mabi=ilp32 -o example.o -e _start -g -no-pie
To dump a binary starting at 0x80000000 that can be directly loaded by rv as in the above example:
riscv64-unknown-elf-objcopy -g -O binary example.o example.bin
Click an instruction to see its implementation in rv.c.
add addi amoadd.w amoand.w amomax.w amomaxu.w amomin.w amominu.w amoor.w amoswap.w amoxor.w and andi auipc beq bge bgtu blt bltu bne c.add c.addi c.addi16spc.and c.andi c.beqz c.bnez c.ebreak c.j c.jal c.jalr c.jr c.li c.lui c.lw c.lwsp c.mv c.or c.slli c.srai c.srli c.sub c.sw c.swsp c.xor csrrc csrrci csrrs csrrsi csrrw csrrwi div divu ebreak ecall fence fence.i jal jalr lb lbu lh lhu lr.w lui lw mret mul mulh mulhsu mulhu or ori rem remu sb sc.w sfence.vmash sll slli slt slti sltiu sltu sra srai sret srl srli sub sw wfi xor xori rv was written in a way that takes maximal advantage of RISCV's instruction orthogonality.rv also tries to strike a good balance between conciseness and readability.break statements using these would result in more bloated code in the author's opinion. As it turns out, you are actually free to reimplement this code with switch statements. See LICENSE.txt.No open issues yet, or sync has not completed.