change request: [HDL] Random Generator

Hi Team,

attached example ("reset" = "0" and "enable" = "1") clamped to the random generator can potentially generate only 0s if loaded onto FPGA Hardware unlike the simulation suggests. The reason is an uninitialized control register at Startup (s_resetReg), which leaves the compiler and/or electrical state of the hardware decide how to proceed. As a consequence the component will never get initialized.

Adding a default value to s_resetReg in the declaration section, i.e. "001", will make this implementation safe.

Where the above suggestion is an immediate fix, we might want to take this further and rewrite the behaviour section slightly so mechanics become less complex.

I have attached an example for consideration.

As a side note it should also be mentioned, the entry "Seed" in the attribute section is never being read and hence has no effect.

Thanks

rng_fail.zip