`embassy-stm32`: 7E1 Uart read includes parity

I've just ran into the issue that I was receiving malformed data with an Uart configured as follows:

        let mut config = Config::default();
        config.baudrate = 1200;
        config.data_bits = DataBits::DataBits7;
        config.stop_bits = StopBits::STOP1;
        config.parity = Parity::ParityEven;

Caused by the MSB of each data byte being the parity bit. This behaviour is documented in the reference manual in my case for the stm32wl55cc as follows:

Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 292).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

Which was unexpected for as a consumer of the Uart impl as parity is an Uart specific implementation detail which shouldn't leak in this way(thats what the parity error is for).

This behavior should at least be documented or the parity bit should be stripped(set to 0) by default imo.