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#2015·capstone

`auto-sync` progress tracker: Refactor and implement architectures

Author: Rot127Created May 9, 2023Updated Aug 13, 2026
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Note to x86: x86 is not part of this list, because we can not generate all tables in C. Refer to https://github.com/capstone-engine/llvm-capstone/issues/13 for details.

Note about changes introduced with auto-sync: For a preview what changes will come in v6, please take a look at the WIP release guide.

This issue tracks the auto-sync refactoring and implementation effort of architecture modules.

The table below lists the responsible developers for each architecture.

To update

Arch CS PR llvm-capstone PR Part of (planned) release Assigned developer(s) LLVM repo
Alpha - - v6 - alphalinux

In progress

Arch CS PR llvm-capstone PR Part of (planned) release Assigned developer(s) Based on LLVM repo
WASM https://github.com/capstone-engine/capstone/pull/2816 - v6 - LLVM repo

.td edits upstreamed

Most LLVM td files miss some information about instructions (memory read/writes, operands incorrectly assigned as in/out etc.). Since we rely on this we need to fix it. Those fixes should be upstreamed to LLVM.

Done

Arch PR Part of release Assigned developer(s) LLVM repo
Alpha https://github.com/capstone-engine/capstone/pull/2071 v6 @R33v0LT LLVM-project (release v3.0)
ARC https://github.com/capstone-engine/capstone/pull/2570 v6 @R33v0LT LLVM-project
AArch64 https://github.com/capstone-engine/capstone/pull/2026 v6 @Rot127 LLVM-project
ARM https://github.com/capstone-engine/capstone/pull/1949 v6 @Rot127 LLVM-project
PPC https://github.com/capstone-engine/capstone/pull/2013 v6 @Rot127 LLVM-project
TriCore https://github.com/capstone-engine/capstone/pull/1973/ v5 @imbillow TriDis
HPPA https://github.com/capstone-engine/capstone/pull/2265 v6 @R33v0LT Not Auto-sync based
LoongArch https://github.com/capstone-engine/capstone/pull/2349 v6 @jiegec LLVM-project
MIPS https://github.com/capstone-engine/capstone/pull/2410 v6 @wargio LLVM-project
SystemZ https://github.com/capstone-engine/capstone/pull/2462 v6 @Rot127 LLVM-project
Xtensa https://github.com/capstone-engine/capstone/pull/2380 v6 @imbillow LLVM-project
BPF https://github.com/capstone-engine/capstone/pull/2568 v6 @Roeegg2 RFC, Linux kernel docs
SPARC https://github.com/capstone-engine/capstone/pull/2704 v6 @Rot127 LLVM-project
RISCV https://github.com/capstone-engine/capstone/pull/2756 v6 @moste00 LLVM-project
M68k https://github.com/capstone-engine/capstone/pull/2880 v6 @b1llow Not Auto-sync based

Arch extensions

Adding CPU extensions which are not part of upsteram LLVM is easier now. Here are they tracked.

Arch Extension name issue previous attempt/notes Done
PPC VLE https://github.com/capstone-engine/capstone/issues/2241 https://lists.llvm.org/pipermail/llvm-dev/2014-July/074613.html No
PPC PS (Paired-Single) None https://reviews.llvm.org/D85137 Yes
Mips NanoMips None Mediatek LLVM: https://github.com/MediaTek-Labs/llvm-project/tree/mtk-pub/nanomips-llvm16, more context: https://github.com/rizinorg/ideas/issues/5 Yes
Mips EE None Not in LLVM, see: https://github.com/capstone-engine/capstone/issues/940#issuecomment-2315690327 No

Effort level of not refactored/implemented archs

Arch Number of operand groups Generates Note Implementation type Difficulty level
AVR ~3 Yes None New Easy
CSKY ~7 Yes None New Medium
DirectX ~1 Yes Deviates from common design. New Medium-Hard
EVM ~2 Not tested Very small module, llvm repo: https://github.com/etclabscore/evm_llvm New Easy
Hexagon ~2 No Deviates from common design. New Hard
Lanai ~10 Yes None New Easy
MSP430 ~6 Yes None New Easy
SPIRV ~9 No td files faulty New Medium
VE ~8 Yes None New Medium
XCore ~15 No td files faulty Refactor Medium

Note to RISC-V: RISC-V will not be generated via LLVM because the LLVM architecture definitions are not precise enough for our use case. Instead, a SAIL based generator will be used (https://github.com/capstone-engine/capstone/issues/2392). RiscV is now updated via Auto-Sync as well. See the table above.

Legend

  • Number of operand groups: Operand groups which have a distinct print functions. Indicates effort to implement the LLVM <-> CS mapping code (fill cs_detail and the like).
  • Generates: inc files generate with most recent backends.
  • Note: Worthy to note.
  • Implementation type: Refactor current implementation or implement new arch module.
  • Difficulty level: Guessed difficulty of this arch (base on points above and complexity like number of instructions etc.). Though "Easy" still means you have to familiarize yourself how LLVM definitions and the updater work. My guess is it will take at least a week of work.

Getting started

  • If you like to refactor an architecture module or implement a new one, please comment here and we add you. Also we can give hints to important information.
  • Please add a draft PR once you've done the first commit, so the progress is visible and there is a place for discussion.
  • Please refer to the auto-sync documentation to learn how to refactor or implement an architecture with auto-sync

TODO for refactored archs

List of missing things which should be done before v6 to get a nice round package.

Capstone

LLVM revisions

Auto-Sync

  • add refactor setting to auto-sync updater.
  • Add auto-sync unit tests
  • Translate template functions as functions, not as macros.

Backends

  • Generate decoding/printing macros as functions, if there is only a single version (allows proper debugging, which would be a blessing).

ARM

  • Add general alias and alias operand handling.
  • Add vector layout information
  • Set post_index when base regsister is tied. Just to make sure to hit every case.
  • Encoding info
  • Move data type insn mapping to own auto-sync class.
  • https://github.com/capstone-engine/capstone/issues/2193

PPC

  • Encoding info

AArch64

  • Encoding info

Source: capstone-engine/capstone

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