awesome-opensource-hardware

awesome-opensource-hardware

A curated list of awesome open source hardware tools, generators, and reusable designs.

• Categorized
• Alphabetical (per category)
• Requirements
  • link should be to source code repository
  • open source projects only
  • working projects only (not WIP/rusty)
• One tag line sentence per project

Table of Contents

PDKs

• Manufacturable PDKs
• Virtual PDKs

Compilers

• Build systems
• Circuit compilers
• FPGA compilers
• Layout compilers

Project

• Documentation

Design and Verification Tools

• Benchmarks
• Board design
• Digital design
• FPGA design
• Formal verification
• Linters
• Register design
• Schematics
• Simulators
• Verification frameworks
• Physics
• Waveform Viewers

Designs & Generators

• Accelerators
• AIB
• AXI
• Analog circuits
• Chip packaging
• Boards
• Connectivity
• CPUs
• FPGA architectures
• Libraries
• Memory
• Systems

Education

• Analog design
• ASIC design
• Digital design
• FPGA design

PDKs

Manufacturable PDKs

• gf180
  • GlobalFoundries 180nm CMOS PDK
• sg13g2
  • IHP 130nm BiCMOS PDK
• sky130
  • Skywater 130nm CMOS PDK

Virtual PDKs

• asap7
  • Predictive 7nm PDK
• freepdk45
  • Predictive 45nm PDK
• probe3.0
  • Process/design DTCO path finding technology

AI

• AnalogCoder
• Analog Circuit Design via Training-Free Code Generation
• hagent
• hardware agent
• Masala-CHAI
• Large-Scale SPICE Netlist Dataset for Analog Circuits

Compilers

Build Systems

• bazelhdl
  • Bazel based hdl build system
• bender
  • Dependency management tool for hardware projects.
• chipyard
  • Agile RISC-V SoC Design Framework.
• cocoon
  • Infrastructure for integrated EDA
• edalize
  • Abstraction library for interfacing EDA tools.
• flgen
  • Generate a filelist for EDA tools
• fusesoc
  • Package manager and build abstraction tool for FPGA/ASIC development.
• hammer
  • Agile physical design component part of UC Berkeley Chipyard framework.
• hbs
  • Tcl-based, minimal common abstraction build system for hardware design projects.
• hwtbuildsystem
  • Library of utils for interaction with the vendor tools.
• mflowgen
  • Build-system generator for ASIC and FPGA design-space exploration.
• orbit
  • Package manager and build tool for HDLs
• siliconcompiler
  • Python based build system and package manager for hardware.
• SoCMake
  • Hardware and software build system and package manager based on CMake

Circuit Compilers

• abc
  • System for sequential logic synthesis and formal verification
• act
  • Asynchronous circuit compiler tools
• aihwkit
  • IBM Analog Hardware Acceleration Kit
• amaranth
  • Python based hardware design framework
• bigspicy
  • Tool for merging circuit descriptions
• bsc
  • Compiler, simulator, and tools for the Bluespec Hardware Description Language
• calyx
  • Intermediate language and compilers that generate custom hardware accelerators
• chisel
  • Scala based hardware description language
• circt
  • Circuit IR Compilers and Tools
• circuitgraph
  • Tools for working with circuits as graphs in python
• circuitops
  • Infrastructure for dataset generation and model deployment in Generative AI
• clash
  • Haskell to VHDL/Verilog/SystemVerilog compiler
• coreir
  • LLVM-style hardware compiler with first class support for generators
• dfiant
  • Dataflow Hardware Description Language
• fault
  • Design-for-testing (DFT) Solution
• finn
  • Dataflow compiler for QNN inference
• firrtl
  • Intermediate Representation for RTL
• gamma
  • Optimizes mapping of DNN models on DNN Accelerators
• gamora
  • Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks
• ghdl-yosys-plugin
  • VHDL synthesis (based on ghdl)
• halide
  • Language for fast, portable data-parallel computation
• halide-to-hardware
  • Hardware generator combining halide and coreir
• hastlayer
  • VHDL generator from .NET languages (C#, F#, and others) and FPGA framework for .NET hardware acceleration
• hdl21
  • Hardware Description Library
• hdlconvertor
  • Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4
• hs-to-coq
  • Convert Haskell source code to Coq source code
• ipyxact
  • Python-based IP-XACT parser
• livehd
  • Infrastructure for live interactive synthesis and simulation
• llhd
  • Intermediate representation for digital circuit descriptions
• lsoracle
  • Famework built on EPFL logic synthesis libraries.
• lstools
  • Showcase examples for EPFL logic synthesis libraries
• kami
  • Platform for High-Level Parametric Hardware Specification and Verification
• magma
  • Python based hardware design language
• matchlib
  • Synthesizable SystemC/C++ library of commonly-used hardware functions
• matchclib_connections
  • Synthesizable SystemC library implementing latency-insensitive channels
• mockturtle
  • C++ logic network library
• myhdl
  • Python based hardware description and verification language
• naja
  • Structural Netlist API for EDA post synthesis flow development
• netlist-paths
  • A library and command-line tool for querying a Verilog netlist
• panda-bambu
  • High level synthesis (HLS) C/C++ framework
• pipelinec
  • C-like hardware description language (HDL) with automatic pipelining
• pygears
  • Python based hardware design framework
• pymtl3
  • Python hardware generation, simulation, and verification framework
• pyrtl
  • Python integrated design and simulation framework
• pysysc
  • Python package to make SystemC usable from Python
• pyverilog
  • Python design toolkit for Verilog HDL
• rohd
  • Dart based framework for describing and verifying hardware
• scip
  • Solving Constraint Integer Problems
• silice
  • Language that simplifies prototyping and writing algorithms on FPGA architectures
• skidl
  • SKiDL is a module that extends Python with the ability to design electronic circuits
• slang
  • Library for lexing, parsing, type checking, and elaborating SystemVerilog code
• sodaopt
  • Optimizer leveraging mlir to extract, optimize, translate HLSinto LLVM IR
• spinalhdl
  • Scala based HDL
• spydrnet
  • Framework for analyzing and transforming Verilog netlists
• surelog
  • SystemVerilog IEEE 2017 Pre-processor, Parser, Elaborator, UHDM Compiler
• sv-parser
  • SystemVerilog IEEE 1800-2017 parser library
• sv2v
  • SystemVerilog to Verilog conversion
• systemc
  • SystemC system design and verification language that spans hardware and software
• systemc-compiler
  • Translates synthesizable SystemC to synthesizable Verilog
• synlig
  • SystemVerilog support for Yosys
• tapasco
  • Heterogeneous system composer
• tce
  • Application-specific instruction-set processor (ASIP) toolset
• uhdm
  • Universal object model for IEEE SystemVerilog designs
• verible
  • SystemVerilog developer tools, including a parser, style-linter, and formatter
• veriloggen
  • Mixed-Paradigm Hardware Construction Framework
• veryl
  • Modern Hardware Description Language based on Rust/SV
• verik
  • Kotlin based hardware description language
• vlsir
  • Interchange formats for chip design
• xls
  • Google framework for hardware synthesis
• yosys
  • Yosys Open SYnthesis Suite

FPGA Compilers

• amf-placer
  • Timing-driven analytical mixed-size FPGA placer
• dreamplacefpga
  • Analytical Placer for Large Scale Heterogeneous FPGA
• flowtune
  • FPGA synehsis and PNR optimizer
• [nextpnr](https://github.com/YosysHQ